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Errata and revision differences

RevisionChanges
V1.5Adds a dedicated PSRAM LDO rail, which makes the 32 MiB PSRAM configuration possible; this revision targets the 32 MiB build; the microSD card-detect pull-down R11 changed from 10 kΩ to 1 kΩ (PF6).
V1.4Corrects the PD pin silkscreen numbering, see the V1.3 errata below. When using only the 16 MiB configuration, changing R11 to 1 kΩ on V1.4 is enough.
V1.3Initial release.

F101S3 has no PD10 and PD11. The V1.3 PCB kept numbering consecutively after PD9, which makes every PD silkscreen label from PD10 onwards two lower than the real SoC GPIO number. This is an identification error in the V1.3 silkscreen, and V1.4 corrects it. When doing pinmux, writing software or reading the schematic, use the “Actual SoC GPIO / V1.4 silkscreen” column in the table below.

V1.3 silkscreenActual SoC GPIO / V1.4 silkscreenEffect
PD10PD12MUX selection must use PD12
PD11PD13MUX selection must use PD13
PD12–PD20PD14–PD22Each corresponding label is offset by +2

Pay particular attention to this on V1.3 boards when configuring functions that pass through these pins, such as display, LVDS/DSI and UART2/4/5. The full mapping table is in Pinout.

V1.4 and earlier: microSD card-detect (CD) pull-down too large

Section titled “V1.4 and earlier: microSD card-detect (CD) pull-down too large”

The microSD card-detect signal is PF6, pulled down by R11. On V1.4 and earlier boards R11 is 10 kΩ, which is too high for the pin to settle reliably below the logic-low threshold, so card insertion may not be detected.

  • Software workaround: set PF6’s output drive strength to its lowest setting in pinctrl.
  • Hardware fix: change R11 to 1 kΩ (V1.5 already does this).
SymptomPossible cause
On V1.3, nothing happens after configuring PD12–PD20Silkscreen offset; you should actually use PD14–PD22
The microSD card is inserted but the system does not see itPF6 card-detect problem; handle it as described above
Want 32 MiB PSRAM but it is unstableNeeds the V1.5 PSRAM LDO; V1.4 and earlier will not work